Series : Bridging Software Craftsmanship and Bare-Metal Firmware (Trusted Firmware – A)

Part 1: The Foundations of Firmware Construction Introduction: What is Software Construction? In this inaugural part of our series on Trusted Firmware-A (TF-A), we begin by examining Software Construction, the central, hands-on activity of creating software. While "coding" is often used as a shorthand, true construction involves substantial professional judgment. It is not merely the mechanical…

Platform Firmware Resilience – (Part – 4)

Firmware Update Mechanisms Firmware protection requires that only authentic and authorized firmware updates be applied to platform devices. Firmware update mechanisms must check for both authenticity (that the update comes from a trusted source) and authorization (that updates are allowed by the system owner). These mechanisms are divided into authenticated update mechanisms and authorized update…

Platform Firmware Resilience – (Part -3)

Platform and Software: High-Level Overview Platform Definition: The platform includes hardware and firmware necessary to initialize the system, boot it, and provide runtime services. Components: Host Processor Boot Firmware: Traditionally known as BIOS, now commonly UEFI. Other Firmware-Enabled Devices: Storage and network controllers. Graphics processing units (GPUs). Service processors (e.g., Baseboard Management Controllers or BMCs).…

Platform Firmware Resilience – (Part -2)

Recovery Mechanisms This section focuses on recovery mechanisms designed to restore a device's firmware or critical data to a valid state in the event of corruption. Recovery is essential for maintaining the security and functionality of a platform. Below are the key guidelines for implementing effective recovery mechanisms: Recovery of Mutable Code and Firmware Recovery…

RISC V debug musings (Machine Mode)

This series aims to create expertise to debug RISC V processor while doing bare-metal firmware development. In this post we will discuss Machine mode debug capabilities. Machine Mode debug Let's first understand Machine mode registers - mstatus, mepc, mcause, mtval mstatus is a control and status register (CSR) in the RISC-V architecture that controls privileged…