Essentials of RISC V

In the ever-evolving world of processors, a new architecture is making waves: RISC-V (pronounced "risk-five"). But what exactly is RISC-V, and why should you care? In this blog post, we'll break down the essentials of RISC-V, making it easy for beginners to understand its core principles and potential impact. We'll explore its advantages, applications, and…

RISC V debug musings (Machine Mode)

This series aims to create expertise to debug RISC V processor while doing bare-metal firmware development. In this post we will discuss Machine mode debug capabilities. Machine Mode debug Let's first understand Machine mode registers - mstatus, mepc, mcause, mtval mstatus is a control and status register (CSR) in the RISC-V architecture that controls privileged…